1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor integrated circuit device, more particularly, to a method for manufacturing a semiconductor integrated circuit device having a stack gate structure.
2. Description of Related Art
A conventional method for manufacturing an EPROM (Erasable and Programmable Read Only Memory) having a stack gate structure in which a control gate is formed above a floating gate via an insulating film (to be referred to as an intermediate insulating film hereinafter) is disclosed in, for example, the Japanese Unexamined Patent Publication (JP-A-) 4-10662.
In this method, as shown in FIG. 1A, a peripheral region A and a cell region B are formed after a field oxide film 32 is formed on the surface of a p type silicon substrate 31. Then, an insulating film (tunnel oxide film) 33 is grown on the surface of each region and a polysilicon film 34 for formation of a floating gate is grown all over the surface. Subsequently, phosphorus is doped into the polysilicon film 34 and then the polysilicon film 34 is selectively etched so that the polysilicon film 34 for the floating gate is remaines in the cell region B. The tunnel oxide film 33 is etched using the floating gate 34 as a mask so that the silicon substrate 31 can be exposed in the peripheral region A. Then, thermal oxidation is performed to grow a gate insulating film 36 on the surface of the silicon substrate 31 in the peripheral region A and an intermediate insulating film 35 on the surface of the floating gate 34 in the cell region B.
As shown in FIG. 1B, a polysilicon film for formation of a gate electrode 37 and a control gate 37a is grown all over the surface and phosphorus is introduced into the polysilicon film on which a first protective oxide film 38 is formed to be a 2-layer film. Then, the 2-layer film is patterned in the peripheral region A and the cell region B so that the gate electrode 37 and a first protective oxide film 38 can be formed in the peripheral region A and the control gate 37a and the first protective oxide film 38 can be formed in the cell region B. Then, a resist layer 39 for forming a cell is formed in the cell region B such that the resist layer 39 covers the control gate 37a and the first protecting oxide film 38.
Next, as shown in FIG. 1C, the intermediate insulating film 35 and the floating gate 34 are etched using the resist layer 39 as a mask and then second protecting oxide films 40 are formed on the side surface of the gate electrode 37, the control gate 37a and the floating gate 34 by thermal oxidation. Subsequently, arsenic ions are implanted all over the surface so that n-type diffusion layers 41 are formed on the surface of the silicon substrate 31.
Thereafter, a BPSG interlayer film 42 is grown all over the surface as an interlayer insulating film. It should be noted that although not shown in the figures contact holes are formed on the gate electrode 37, the control gate 37a and the n-type diffusion layers 41 so that the EPROM is completed by formation of aluminum wirings.
In the above method, the insulating film between the floating gate 34a and the control gate 37a, i.e., the intermediate insulating film 35, is formed on the surface by performing the thermal oxidation for the polysilicon film for formation of the floating gate 34. Such an intermediate insulating film 35 formed by the thermal oxidation is not preferable for a highly integrated EPROM because the film 35 becomes thick because of the thermal oxidation for the polysilicon film including impurity and the film thickness control is wrong.
For this reason, intermediate insulating film has been used a laminate film formed by sandwiching a SiN (silicon nitride) film, which is formed by a CVD method, between SiO films (silicon oxide films).
In a case that such a laminate film is employed as the above EPROM intermediate insulating film 35, because the insulating film is unnecessary to the peripheral region A, the surface of the silicon substrate 31 should be exposed in the peripheral region A. Therefore, after the polysilicon film 34 is formed as shown in FIG. 1A, the laminate film is formed all over the surface, then the laminate film is etched using the resist pattern covering the cell region B. Then a gate insulating film 36 is formed by performing thermal oxidation for the surface of the silicon substrate 31 thus exposed.
However, if the method is employed, there is caused a problem that when the etching selection ratio of the nitride film against the oxide film thereunder is not great in etching the laminate film constituted of the nitride film and the oxide films, the oxide film is also etched in the peripheral region A in addition to the nitride film to further etch the surface of the silicon substrate 31 so that the surface of the peripheral region A is damaged to cause the leakage in a p-n junction to be formed thereafter. This problem is caused even when the etching selection ratio between the nitride film and the oxide film is great, so that the surface of the silicon substrate in the peripheral region A is damaged because the lower oxide film is thin to be a few tens .ANG. with less etching margin.